The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 15, 2021

Filed:

Dec. 28, 2016
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Robert Alan May, Chandler, AZ (US);

Kristof Kuwawi Darmawikarta, Chandler, AZ (US);

Sri Ranga Sai Boyapati, Chandler, AZ (US);

Sandeep Gaan, Phoenix, AZ (US);

Srinivas V. Pietambaram, Chandler, AZ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/52 (2006.01); H01L 21/48 (2006.01); H01L 23/498 (2006.01); H05K 3/42 (2006.01); H05K 3/38 (2006.01);
U.S. Cl.
CPC ...
H01L 21/4857 (2013.01); H01L 21/481 (2013.01); H01L 23/49822 (2013.01); H01L 23/49866 (2013.01); H05K 3/423 (2013.01); H01L 2224/16225 (2013.01); H01L 2924/15311 (2013.01); H05K 3/38 (2013.01); H05K 2201/096 (2013.01); H05K 2201/09845 (2013.01); H05K 2203/1407 (2013.01); H05K 2203/1476 (2013.01);
Abstract

Integrated circuit (IC) package substrates having high density interconnects with a sputter seed layer containing a copper alloy, as well as related structures, devices, and methods, are disclosed herein. For example, in some embodiments, a package substrate may include a first dielectric layer, a sputter seed layer disposed on the first dielectric layer, wherein the seed layer includes a copper alloy, a patterned conductive layer disposed on the seed layer, and a second dielectric layer over the patterned conductive layer.


Find Patent Forward Citations

Loading…