The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 01, 2021

Filed:

Aug. 09, 2019
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Hung-Wei Liu, Meridian, ID (US);

Sameer Chhajed, Boise, ID (US);

Jeffery B. Hull, Boise, ID (US);

Anish A. Khandekar, Boise, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 27/108 (2006.01); H01L 29/66 (2006.01); H01L 29/04 (2006.01); H01L 21/02 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7841 (2013.01); H01L 21/02686 (2013.01); H01L 27/10802 (2013.01); H01L 29/04 (2013.01); H01L 29/66666 (2013.01); H01L 29/7827 (2013.01);
Abstract

A transistor comprises a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region. At least one of the top source/drain region, the bottom source/drain region, and the channel region are crystalline. All crystal grains within the at least one of the top source/drain region, the bottom source/drain region, and the channel region have average crystal sizes within 0.064 μmof one another. Other embodiments, including methods, are disclosed.


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