The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 01, 2021

Filed:

Apr. 17, 2019
Applicant:

Powertech Technology Inc., Hsinchu County, TW;

Inventors:

Ming-Chih Chen, Hsinchu County, TW;

Hung-Hsin Hsu, Hsinchu County, TW;

Yuan-Fu Lan, Hsinchu County, TW;

Chi-An Wang, Hsinchu County, TW;

Hsien-Wen Hsu, Hsinchu County, TW;

Assignee:

POWERTECH TECHNOLOGY INC., Hsinchu County, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/065 (2006.01); H01L 21/76 (2006.01); H01L 23/31 (2006.01); H01L 21/768 (2006.01); H01L 23/00 (2006.01); H01L 21/56 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); H01L 21/568 (2013.01); H01L 21/76805 (2013.01); H01L 23/3107 (2013.01); H01L 24/08 (2013.01); H01L 24/17 (2013.01); H01L 24/19 (2013.01); H01L 24/20 (2013.01); H01L 24/96 (2013.01); H01L 2224/02371 (2013.01); H01L 2224/32145 (2013.01);
Abstract

A manufacturing method is applied to set a stackable chip package. The manufacturing method includes encapsulating a plurality of chips stacked with each other, disposing a lateral surface of the stacked chips having conductive elements onto a substrate, disassembling the substrate from the conductive elements when the stacked chips are encapsulated, and disposing a dielectric layer with openings on the stacked chips to align the openings with the conductive elements for ball mounting process.


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