The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 25, 2021

Filed:

Oct. 07, 2019
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Tsung-Shu Lin, New Taipei, TW;

Wensen Hung, Zhubei, TW;

Hung-Chi Li, Taipei, TW;

Tsung-Yu Chen, Hsinchu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/78 (2006.01); H01L 23/367 (2006.01); H01L 25/065 (2006.01); H01L 25/00 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 23/31 (2006.01); H01L 23/498 (2006.01);
U.S. Cl.
CPC ...
H01L 23/3677 (2013.01); H01L 21/4853 (2013.01); H01L 21/4882 (2013.01); H01L 21/561 (2013.01); H01L 21/565 (2013.01); H01L 21/78 (2013.01); H01L 23/3135 (2013.01); H01L 23/367 (2013.01); H01L 23/3675 (2013.01); H01L 25/0652 (2013.01); H01L 25/50 (2013.01); H01L 23/3128 (2013.01); H01L 23/49827 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/92125 (2013.01); H01L 2224/97 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06544 (2013.01); H01L 2225/06558 (2013.01); H01L 2225/06582 (2013.01); H01L 2225/06589 (2013.01); H01L 2924/10155 (2013.01); H01L 2924/10158 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/181 (2013.01);
Abstract

In an embodiment, a device includes: a die stack over and electrically connected to an interposer, the die stack including a topmost integrated circuit die including: a substrate having a front side and a back side opposite the front side, the front side of the substrate including an active surface; a dummy through substrate via (TSV) extending from the back side of the substrate at least partially into the substrate, the dummy TSV electrically isolated from the active surface; a thermal interface material over the topmost integrated circuit die; and a dummy connector in the thermal interface material, the thermal interface material surrounding the dummy connector, the dummy connector electrically isolated from the active surface of the topmost integrated circuit die.


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