The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 25, 2021

Filed:

Aug. 20, 2019
Applicant:

Infineon Technologies Dresden Gmbh & Co. KG, Dresden, DE;

Inventors:

Markus Beninger-Bina, Grosshelfendorf, DE;

Matteo Dainese, Munich, DE;

Ingo Dirnstorfer, Dresden, DE;

Erich Griebl, Dorfen, DE;

Johannes Georg Laven, Taufkirchen, DE;

Anton Mauder, Kolbermoor, DE;

Hans-Joachim Schulze, Taufkirchen, DE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/32 (2006.01); H01L 21/768 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 21/3115 (2006.01); H01L 29/739 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76816 (2013.01); H01L 21/31155 (2013.01); H01L 21/32 (2013.01); H01L 29/66348 (2013.01); H01L 29/66674 (2013.01); H01L 29/7397 (2013.01); H01L 29/7801 (2013.01);
Abstract

A method includes: forming trenches extending from a surface along a vertical direction into a semiconductor body, facing trench sidewalls of two adjacent trenches laterally confining a mesa region of the semiconductor body along a first lateral direction; forming a body region in the mesa region, a surface of the body region in the mesa region at least partially forming the semiconductor body surface; forming a first insulation layer on the semiconductor body surface; subjecting the semiconductor body region to a tilted source implantation using at least one contact hole in the first insulation layer at least partially as a mask for forming a semiconductor source region in the mesa region. The tilted source implantation is tilted from the vertical direction by an angle of at least 10°. The semiconductor source region extends for no more than 80% of a width of the mesa region along the first lateral direction.


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