The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 27, 2021
Filed:
Nov. 30, 2018
Applicant:
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;
Inventors:
Assignee:
TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu, TW;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/092 (2006.01); H01L 21/8238 (2006.01); H01L 29/66 (2006.01); B82Y 10/00 (2011.01); H01L 29/423 (2006.01); H01L 29/775 (2006.01); H01L 29/06 (2006.01); H01L 29/786 (2006.01); H01L 21/02 (2006.01); H01L 21/3115 (2006.01); H01L 21/8258 (2006.01); H01L 29/161 (2006.01); H01L 29/49 (2006.01); H01L 29/51 (2006.01); H01L 29/78 (2006.01); H01L 29/20 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0924 (2013.01); B82Y 10/00 (2013.01); H01L 21/02532 (2013.01); H01L 21/02538 (2013.01); H01L 21/3115 (2013.01); H01L 21/8258 (2013.01); H01L 21/823807 (2013.01); H01L 29/068 (2013.01); H01L 29/0673 (2013.01); H01L 29/161 (2013.01); H01L 29/42392 (2013.01); H01L 29/4966 (2013.01); H01L 29/511 (2013.01); H01L 29/517 (2013.01); H01L 29/66439 (2013.01); H01L 29/66545 (2013.01); H01L 29/775 (2013.01); H01L 29/78696 (2013.01); H01L 21/823821 (2013.01); H01L 21/823828 (2013.01); H01L 29/20 (2013.01); H01L 29/66469 (2013.01); H01L 29/7848 (2013.01);
Abstract
Disclosed is a method for manufacturing a semiconductor device. The method for manufacturing the semiconductor device includes forming a p-channel over a semiconductor substrate. A gate dielectric layer is formed over the p-channel. The gate dielectric layer is doped with a dopant. A first metal gate is formed over the gate dielectric layer.