The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 27, 2021
Filed:
Apr. 05, 2019
Globalfoundries U.s. Inc., Santa Clara, CA (US);
Abu Naser M. Zainuddin, Clifton Park, NY (US);
Christopher D. Sheraw, Severn, MD (US);
Sangameshwar Rao Saudari, Clifton Park, NY (US);
Wei Ma, Clifton Park, NY (US);
Kai Zhao, Latham, NY (US);
Bala S Haran, Watervliet, NY (US);
GLOBALFOUNDRIES U.S. INC., Santa Clara, CA (US);
Abstract
A method includes forming a first region including a pair of first FinFETs and a second region including a pair of second FinFETs on a substrate. Each FinFET includes a metal gate having a first spacer adjacent thereto, and each first FinFET has a gate dielectric that is thicker than a gate dielectric of each second FinFET, such that the first FinFETs can be higher voltage input/output devices. The method forms a first contact between the metal gates of the pair of first FinFETs with a second spacer thereabout, the second spacer contacting a portion of each first spacer. The second spacer thus has a portion extending parallel to the metal gates, and a portion extending perpendicular to the metal gates. A second contact is formed between the metal gates of the pair of second FinFETs, and the second contact devoid of the second spacer.