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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10985179 B1

PDFFull Text
Date of Patent:
Apr. 20, 2021

Filed:

Aug. 05, 2019

Memory arrays and methods used in forming a memory array comprising strings of memory cells and operative through-array-vias

Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Yi Hu, Boise, ID (US);

Merri L. Carlson, Boise, ID (US);

Anilkumar Chandolu, Boise, ID (US);

Indra V. Chary, Boise, ID (US);

David Daycock, Woodhaven, SG;

Harsh Narendrakumar Jain, Boise, ID (US);

Matthew J. King, Boise, ID (US);

Jian Li, Boise, ID (US);

Brett D. Lowe, Boise, ID (US);

Prakash Rau Mokhna Rau, Boise, ID (US);

Lifang Xu, Boise, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:

Wells St. John P.S.

Primary Examiner:

Ly D Pham

Int. Cl.
CPC ...
H01L 27/11582 (2017.01); H01L 27/11556 (2017.01); H01L 27/11565 (2017.01); H01L 21/28 (2006.01); H01L 21/768 (2006.01); H01L 27/115 (2017.01); H01L 21/311 (2006.01); H01L 21/02 (2006.01); H01L 27/11526 (2017.01); H01L 27/11519 (2017.01); H01L 27/11573 (2017.01); H01L 21/3213 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); H01L 21/02532 (2013.01); H01L 21/02595 (2013.01); H01L 21/02636 (2013.01); H01L 21/31111 (2013.01); H01L 21/32133 (2013.01); H01L 27/11519 (2013.01); H01L 27/11526 (2013.01); H01L 27/11556 (2013.01); H01L 27/11565 (2013.01); H01L 27/11573 (2013.01); H01L 21/0217 (2013.01); H01L 29/40114 (2019.08); H01L 29/40117 (2019.08);
Abstract

A method used in forming a memory array comprising strings of memory cells and operative through-array-vias (TAVs) comprises forming a stack comprising vertically-alternating insulative tiers and conductive tiers. The stack comprises a TAV region and an operative memory-cell-string region. The TAV region comprises spaced operative TAV areas. Operative channel-material strings are formed in the stack in the operative memory-cell-string region and dummy channel-material strings are formed in the stack in the TAV region laterally outside of and not within the operative TAV areas. Operative TAVs are formed in individual of the spaced operative TAV areas in the TAV region. Other methods and structure independent of method are disclosed.

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