The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 06, 2021

Filed:

Aug. 29, 2017
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Jackson Chung Peng Kong, Tanjung Tokong, MY;

Bok Eng Cheah, Bayan Lepas, MY;

Khang Choong Yong, Puchong, MY;

Ramaswamy Parthasarathy, Bangalore, IN;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/02 (2006.01); H05K 1/03 (2006.01); H05K 1/11 (2006.01); H05K 1/18 (2006.01); H05K 3/00 (2006.01); H05K 3/10 (2006.01); H05K 3/46 (2006.01); H01P 3/00 (2006.01); H01P 3/08 (2006.01); H03H 7/38 (2006.01); H03H 7/42 (2006.01);
U.S. Cl.
CPC ...
H05K 1/0222 (2013.01); H05K 1/0219 (2013.01); H05K 1/0224 (2013.01); H05K 2201/0707 (2013.01); H05K 2201/09672 (2013.01);
Abstract

Embodiments are generally directed to 3D high-inductive ground plane for crosstalk reduction. An embodiment of a printed circuit board includes a first signal trace and a second signal trace on a first layer, wherein the first signal trace and second signal trace are non-intersecting; a second layer below the first layer; a third layer below the second layer; and a three-dimensional (3D) ground plane, the 3D ground plane including a first plurality of segments on the third layer, a second plurality of segments on the second layer, and a plurality of metal vias to connect the first plurality of segments and the second plurality of segments in the ground plane.


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