The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 23, 2021
Filed:
Feb. 27, 2019
International Business Machines Corporation, Armonk, NY (US);
Ruilong Xie, Niskayuna, NY (US);
Julien Frougier, Albany, NY (US);
Chanro Park, Clifton Park, NY (US);
Edward Nowak, Essex Junction, VT (US);
Yi Qi, Niskayuna, NY (US);
Kangguo Cheng, Schenectady, NY (US);
Nicolas Loubet, Guilderland, NY (US);
INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US);
Abstract
Embodiments of the present invention are directed to techniques for providing an novel field effect transistor (FET) architecture that includes a center fin region and one or more vertically stacked nanosheets. In a non-limiting embodiment of the invention, a nanosheet stack is formed over a substrate. The nanosheet stack can include one or more first semiconductor layers and one or more first sacrificial layers. A trench is formed by removing a portion of the one or more first semiconductor layers and the one or more first sacrificial layers. The trench exposes a surface of a bottommost sacrificial layer of the one or more first sacrificial layers. The trench can be filled with one or more second semiconductor layers and one or more second sacrificial layers such that each of the one or more second semiconductor layers is in contact with a sidewall of one of the one or more first semiconductor layers.