The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 02, 2021

Filed:

Sep. 16, 2019
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Sheng-Tsung Wang, Hsinchu, TW;

Lin-Yu Huang, Hsinchu, TW;

Chia-Lin Chuang, Taoyuan, TW;

Chia-Hao Chang, Hsinchu, TW;

Cheng-Chi Chuang, New Taipei, TW;

Yu-Ming Lin, Hsinchu, TW;

Chih-Hao Wang, Baoshan Township, Hsinchu County, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/49 (2006.01); H01L 29/45 (2006.01); H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 21/764 (2006.01); H01L 21/28 (2006.01);
U.S. Cl.
CPC ...
H01L 29/4991 (2013.01); H01L 21/28123 (2013.01); H01L 21/764 (2013.01); H01L 29/45 (2013.01); H01L 29/6656 (2013.01); H01L 29/66545 (2013.01); H01L 29/66795 (2013.01); H01L 29/7851 (2013.01);
Abstract

A semiconductor device structure includes a gate stack and an adjacent source/drain contact structure formed over a semiconductor substrate. The semiconductor device structure includes a first gate spacer structure extending from a sidewall of the gate stack to a sidewall of the source/drain contact structure, and a second gate spacer structure formed over the first gate spacer structure and between the gate stack and the source/drain contact structure. The second gate spacer structure includes first and second gate spacer layers adjacent to the sidewall of the gate stack and the sidewall of the source/drain contact structure, respectively, and a third gate spacer layer separating the first gate spacer layer from the second gate spacer layer, so that an air gap is sealed by the first, second, and the third gate spacer layers and the first gate spacer structure.


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