The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 02, 2021

Filed:

Aug. 15, 2019
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Marc A. Bergendahl, Troy, NY (US);

Kangguo Cheng, Schenectady, NY (US);

Gauri Karve, Cohoes, NY (US);

Fee Li Lie, Albany, NY (US);

Eric R. Miller, Schenectady, NY (US);

John R. Sporre, Albany, NY (US);

Sean Teehan, Rensselaer, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/12 (2006.01); H01L 21/8234 (2006.01); H01L 21/306 (2006.01); H01L 21/308 (2006.01); H01L 21/762 (2006.01); H01L 29/66 (2006.01); H01L 27/088 (2006.01); H01L 29/06 (2006.01); H01L 21/84 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1207 (2013.01); H01L 21/3081 (2013.01); H01L 21/30604 (2013.01); H01L 21/76224 (2013.01); H01L 21/823431 (2013.01); H01L 21/823437 (2013.01); H01L 21/823481 (2013.01); H01L 21/845 (2013.01); H01L 27/0886 (2013.01); H01L 27/1211 (2013.01); H01L 29/0649 (2013.01); H01L 29/66545 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01);
Abstract

Sub-fin removal techniques for SOI like isolation in finFET devices are provided. In one aspect, a method for forming a finFET device includes: etching partial fins in a substrate, wherein the partial fins include top portions of fins of the finFET device; forming a bi-layer spacer on the top portions of the fins; complete etching of the fins in the substrate to form bottom portions of the fins of the finFET device; depositing an insulator between the fins; recessing the insulator enough to expose a region of the fins not covered by the bi-layer spacer; removing the exposed region of the fins to create a gap between the top and bottom portions of the fins; filling the gap with additional insulator. A method for forming a finFET device is also provided where placement of the fin spacer occurs after (rather than before) insulator deposition. A finFET device is also provided.


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