The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 02, 2021

Filed:

Dec. 12, 2019
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Li-Sheng Weng, Chandler, AZ (US);

Chung-Hao Joseph Chen, Portland, OR (US);

Emile Davies-Venn, Gilbert, AZ (US);

Kemal Aygun, Tempe, AZ (US);

Mitul B. Modi, Phoenix, AZ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/538 (2006.01); H01L 23/552 (2006.01); H01L 25/065 (2006.01); H01L 21/48 (2006.01); H01L 23/66 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5383 (2013.01); H01L 23/552 (2013.01); H01L 25/0655 (2013.01); H01L 21/4857 (2013.01); H01L 23/66 (2013.01); H01L 2223/6677 (2013.01); H01L 2224/18 (2013.01); H01L 2924/15192 (2013.01);
Abstract

Disclosed is a microelectronics package. The microelectronics package may include a reference plane, a signal routing layer, a dielectric layer, and a conductive layer. The signal routing layer may include a plurality of signal routing traces. The dielectric layer may be located adjacent to the signal routing layer. The conductive layer may be applied to the dielectric layer such that the dielectric layer is located in between the signal routing layer and the conductive layer. The conductive layer may be in electrical communication with the reference plane.


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