The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 26, 2021
Filed:
Feb. 27, 2019
International Business Machines Corporation, Armonk, NY (US);
Ruilong Xie, Niskayuna, NY (US);
Julien Frougier, Albany, NY (US);
Chanro Park, Clifton Park, NY (US);
Edward Nowak, Essex Junction, VT (US);
Yi Qi, Niskayuna, NY (US);
Kangguo Cheng, Schenectady, NY (US);
Nicolas Loubet, Guilderland, NY (US);
INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US);
Abstract
Embodiments of the present invention are directed to techniques for providing an novel field effect transistor (FET) architecture that includes a center fin region and one or more vertically stacked nanosheets. In a non-limiting embodiment of the invention, a non-planar channel region is formed having a first semiconductor layer, a second semiconductor layer, and a fin-shaped bridge layer between the first semiconductor layer and the second semiconductor layer. Forming the non-planar channel region can include forming a nanosheet stack over a substrate, forming a trench by removing a portion of the nanosheet stack, and forming a third semiconductor layer in the trench. Outer surfaces of the first semiconductor layer, the second semiconductor layer, and the fin-shaped bridge region define an effective channel width of the non-planar channel region.