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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10886130 B1

PDFFull Text
Date of Patent:
Jan. 05, 2021

Filed:

Aug. 24, 2018

Methods of forming crystalline semiconductor material, and methods of forming transistors

Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Manuj Nahar, Boise, ID (US);

Darwin Franseda Fan, Boise, ID (US);

Junting Liu-Norrod, Boise, ID (US);

Michael Mutch, Boise, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:

Wells St. John P.S.

Primary Examiner:

Shouxiang Hu

Int. Cl.
CPC ...
H01L 21/76 (2006.01); H01L 21/20 (2006.01); H01L 21/02 (2006.01); C23C 16/56 (2006.01); H01L 21/306 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 27/108 (2006.01); C23C 16/24 (2006.01); C23C 16/06 (2006.01); H01L 27/24 (2006.01);
U.S. Cl.
CPC ...
H01L 21/2022 (2013.01); C23C 16/06 (2013.01); C23C 16/24 (2013.01); C23C 16/56 (2013.01); H01L 21/0245 (2013.01); H01L 21/0262 (2013.01); H01L 21/0265 (2013.01); H01L 21/02422 (2013.01); H01L 21/02513 (2013.01); H01L 21/02532 (2013.01); H01L 21/02592 (2013.01); H01L 21/02595 (2013.01); H01L 21/02636 (2013.01); H01L 21/02661 (2013.01); H01L 21/02667 (2013.01); H01L 21/30604 (2013.01); H01L 27/10805 (2013.01); H01L 27/2454 (2013.01); H01L 29/66666 (2013.01); H01L 29/7827 (2013.01);
Abstract

Some embodiments include a method of forming crystalline semiconductor material. A template is provided to have a polycrystalline region along a surface. Semiconductor material is deposited along the surface under conditions which grow crystalline semiconductor structures from grains of the polycrystalline region. The deposition is conducted at a temperature of less than or equal to 500° C. Some embodiments include a method of forming a transistor. A template is provided to have a polycrystalline region along a surface. Semiconductor material is deposited along the surface under conditions which grow crystalline semiconductor structures from grains of the polycrystalline region. The semiconductor material includes germanium. The crystalline semiconductor structures are doped to form a configuration having a first portion over a second portion. Insulative material is formed adjacent the second portion. A transistor gate is formed along the insulative material.

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