The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 29, 2020

Filed:

Apr. 18, 2019
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Inventors:

Wen-De Wang, Minsyong Township, TW;

Dun-Nian Yaung, Taipei, TW;

Jen-Cheng Liu, Hsinchu, TW;

Chun-Chieh Chuang, Tainan, TW;

Jeng-Shyan Lin, Tainan, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/00 (2006.01); H01L 27/146 (2006.01); H01L 23/48 (2006.01);
U.S. Cl.
CPC ...
H01L 27/14636 (2013.01); H01L 23/481 (2013.01); H01L 27/1464 (2013.01); H01L 27/14621 (2013.01); H01L 27/14683 (2013.01);
Abstract

An image sensor device includes a pixel array, a control circuit, an interconnect structure, and a conductive layer. The pixel array is disposed on a device substrate within a pixel region. The control circuit disposed on the device substrate within a circuit region, the control circuit being adjacent and electrically coupled to the pixel array. The interconnect structure overlies and electrically connects the control circuit and the pixel array. The interconnect structure includes interconnect metal layers separated from each other by inter-metal dielectric layers and vias that electrically connect between metal traces of the interconnect layers. The conductive layer disposed over the interconnect structure and electrically connected to the interconnect structure by an upper via disposed through an upper inter-metal dielectric layer therebetween. The conductive layer extends laterally within outermost edges of the interconnect structure and within the pixel region and the circuit region.


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