The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 29, 2020

Filed:

Jul. 15, 2019
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Chin-Yu Lin, Taichung, TW;

Keng-Ying Liao, Tainan, TW;

Huai-Jen Tung, Tainan, TW;

Po-Zen Chen, Tainan, TW;

Su-Yu Yeh, Tainan, TW;

Chia-Yun Chen, Taipei, TW;

Ta-Cheng Wei, Tainan, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/00 (2006.01); H01L 21/00 (2006.01); H01L 31/00 (2006.01); H01L 27/146 (2006.01); H01L 21/306 (2006.01); H01L 21/762 (2006.01); H01L 21/768 (2006.01); H01L 31/18 (2006.01); H01L 21/3105 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1463 (2013.01); H01L 21/30604 (2013.01); H01L 21/31053 (2013.01); H01L 21/76224 (2013.01); H01L 21/76895 (2013.01); H01L 27/14683 (2013.01); H01L 31/1804 (2013.01);
Abstract

A method for fabricating a semiconductor device is provided. The method includes forming a metal catalyst layer on an etching area of the semiconductor substrate; performing a wet etch process to the semiconductor substrate to etch the etching area of the semiconductor substrate under the metal catalyst layer, thereby forming a trench in the semiconductor substrate; and removing the metal catalyst layer from the semiconductor substrate after performing the wet etch process.


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