The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 29, 2020
Filed:
Jun. 02, 2017
Taiwan Semiconductor Manufacturing Company Limited, Hsinchu, TW;
Chih-Liang Chen, Hsinchu, TW;
Cheng-Chi Chuang, New Taipei, TW;
Chih-Ming Lai, Hsinchu, TW;
Chia-Tien Wu, Taichung, TW;
Charles Chew-Yuen Young, Cupertino, CA (US);
Jiann-Tyng Tzeng, Hsinchu, TW;
Kam-Tou Sio, Hsinchu County, TW;
Ru-Gun Liu, Hsinchu County, TW;
Wei-Cheng Lin, Taichung, TW;
Lei-Chun Chou, Taipei, TW;
Taiwan Semiconductor Manufacturing, Hsinchu, TW;
Company Limited, Hsinchu, TW;
Abstract
A self aligned via and a method for fabricated a semiconductor device using a double-trench constrained self alignment process to form the via. The method includes forming a first trench and depositing a first metal into the first trench. Afterwards, the process includes depositing a dielectric layer over the first metal such that a top surface of the dielectric layer is at substantially the same level as the top surface of the first trench. Next, a second trench is formed and a via is formed by etching the portion of the dielectric layer exposed by the overlapping region between the first trench and the second trench. The via exposes a portion of the first metal and a second metal is deposited into the second trench such that the second metal is electrically coupled to the first metal.