The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 29, 2020

Filed:

Sep. 14, 2015
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Tessil Thomas, Bangalore, IN;

Robin A. Steinbrecher, Olympia, WA (US);

Sandeep Ahuja, University Place, WA (US);

Michael Berktold, Phoenix, AZ (US);

Timothy Y. Kam, Portland, OR (US);

Howard Chin, Westford, MA (US);

Phani Kumar Kandula, Bangalore, IN;

Krishnakanth V. Sistla, Beaverton, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/30 (2006.01); G06F 1/20 (2006.01); G06F 1/3296 (2019.01); G06F 1/3206 (2019.01); G06F 1/324 (2019.01); G06F 3/041 (2006.01); G06F 1/26 (2006.01); G06F 1/32 (2019.01);
U.S. Cl.
CPC ...
G06F 1/206 (2013.01); G06F 1/20 (2013.01); G06F 1/324 (2013.01); G06F 1/3206 (2013.01); G06F 1/3296 (2013.01); G06F 3/0412 (2013.01); G06F 11/3058 (2013.01); G06F 1/26 (2013.01); G06F 1/266 (2013.01); G06F 1/32 (2013.01); Y02D 10/00 (2018.01);
Abstract

In an embodiment, a processor includes at least one core and power management logic. The power management logic is to receive temperature data from a plurality of dies within a package that includes the processor, and determine a smallest temperature control margin of a plurality of temperature control margins. Each temperature control margin is to be determined based on a respective thermal control temperature associated with the die and also based on respective temperature data associated with the die. The power management logic is also to generate a thermal report that is to include the smallest temperature control margin, and to store the thermal report. Other embodiments are described and claimed.


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