The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 22, 2020

Filed:

Oct. 25, 2018
Applicant:

Sj Semiconductor(jiangyin) Corporation, Jiangyin, CN;

Inventors:

Yenheng Chen, Jiangyin, CN;

Chengchung Lin, Jiangyin, CN;

Jangshen Lin, Jiangyin, CN;

Chengtar Wu, Jiangyin, CN;

Chihon Ho, Jiangyin, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01Q 11/08 (2006.01); H01L 23/66 (2006.01); H01L 23/522 (2006.01); H01L 23/00 (2006.01); H01Q 1/22 (2006.01); H01L 21/56 (2006.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
H01L 23/66 (2013.01); H01L 21/56 (2013.01); H01L 23/3114 (2013.01); H01L 23/5226 (2013.01); H01L 24/08 (2013.01); H01L 24/11 (2013.01); H01L 24/13 (2013.01); H01Q 1/2283 (2013.01); H01L 2223/6677 (2013.01); H01L 2224/0231 (2013.01); H01L 2224/02379 (2013.01); H01L 2224/0401 (2013.01);
Abstract

The present disclosure provides a fan-out antenna packaging structure and a method for preparing the same. The fan-out antenna packaging structure comprises: a semiconductor chip; a plastic packaging material layer comprising a first surface and an opposite second surface, wherein the plastic packaging material layer packages a periphery of the semiconductor chip; a metal connecting pole located in the plastic packaging material layer and running through the plastic packaging material layer from top to bottom; an antenna structure located on the first surface of the plastic packaging material layer and electrically connected with the metal connecting pole; are distribution layer located on the second surface of the plastic packaging material layer and electrically connected with the semiconductor chip and the metal connecting pole; and a solder bump located on a surface, insulated from the plastic packaging material layer, of the redistribution layer, and electrically connected with the redistribution layer.


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