The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 15, 2020

Filed:

Sep. 13, 2019
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Hao-Juin Liu, Kaohsiung, TW;

Chita Chuang, Hsinchu, TW;

Yao-Chun Chuang, Hsinchu, TW;

Ming Hung Tseng, Toufen Township, TW;

Chen-Shien Chen, Zhubei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 21/48 (2006.01); H01L 23/49 (2006.01); H01L 23/538 (2006.01); H01L 23/13 (2006.01); H05K 1/11 (2006.01); H05K 1/02 (2006.01); H01L 23/498 (2006.01);
U.S. Cl.
CPC ...
H01L 21/4821 (2013.01); H01L 21/4825 (2013.01); H01L 21/4842 (2013.01); H01L 21/4853 (2013.01); H01L 23/13 (2013.01); H01L 23/49816 (2013.01); H01L 23/49838 (2013.01); H01L 23/49894 (2013.01); H01L 23/5384 (2013.01); H01L 24/13 (2013.01); H01L 24/16 (2013.01); H01L 24/81 (2013.01); H05K 1/0296 (2013.01); H05K 1/112 (2013.01); H01L 2224/13147 (2013.01); H01L 2224/13564 (2013.01); H01L 2224/13601 (2013.01); H01L 2224/13611 (2013.01); H01L 2224/13624 (2013.01); H01L 2224/13639 (2013.01); H01L 2224/13644 (2013.01); H01L 2224/13647 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/81191 (2013.01); H01L 2224/81193 (2013.01); H01L 2224/81815 (2013.01); H01L 2924/014 (2013.01); H01L 2924/0133 (2013.01); H01L 2924/181 (2013.01); H01L 2924/351 (2013.01); Y10T 29/49149 (2015.01);
Abstract

A method includes forming a plurality of vias in a dielectric layer and over a package substrate and forming a plurality of top pads over the dielectric layer, each of the plurality of top pads being connected to a respective via of the plurality of vias, wherein the plurality of top pads includes a first group, a second group, a third group and a fourth group, wherein the first group is separated from the fourth group by a first pad line, wherein the first group is separated from the second group by a second pad line, the first pad line comprising a plurality of first elongated pads, the second pad line comprising a plurality of second elongated pads, the second pad line being orthogonal to the first pad line.


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