The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 15, 2020

Filed:

Sep. 21, 2018
Applicant:

Yangtze Memory Technologies Co., Ltd., Wuhan, CN;

Inventors:

Jun Chen, Wuhan, CN;

Jifeng Zhu, Wuhan, CN;

Zhenyu Lu, Wuhan, CN;

Yushi Hu, Wuhan, CN;

Jin Wen Dong, Wuhan, CN;

Lan Yao, Wuhan, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11582 (2017.01); G11C 16/04 (2006.01); G11C 13/00 (2006.01); H01L 25/065 (2006.01); H01L 27/24 (2006.01);
U.S. Cl.
CPC ...
G11C 16/0483 (2013.01); G11C 13/0069 (2013.01); G11C 16/0466 (2013.01); H01L 25/0652 (2013.01); H01L 25/0657 (2013.01); H01L 27/2481 (2013.01);
Abstract

Embodiments of three-dimensional (3D) memory devices are disclosed. In an example, a 3D memory device includes a substrate, a peripheral device disposed on the substrate, a memory stack disposed above the peripheral device and including a plurality of conductor/dielectric layer pairs, and a plurality of memory strings. Each of the memory strings extends vertically through the memory stack and includes a drain select gate and a source select gate above the drain select gate. Edges of the conductor/dielectric layer pairs in a staircase structure of the memory stack along a vertical direction away from the substrate are staggered laterally toward the memory strings.


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