The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 08, 2020
Filed:
Dec. 11, 2018
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;
Chih-Liang Chen, Hsinchu, TW;
Chih-Ming Lai, Hsinchu, TW;
Charles Chew-Yuen Young, Cupertino, CA (US);
Chi-Yeh Yu, Hsinchu, TW;
Jiann-Tyng Tzeng, Hsin Chu, TW;
Kam-Tou Sio, Zhubei, TW;
Pin-Dai Sue, Tainan, TW;
Ru-Gun Liu, Zhubei, TW;
Shih-Wei Peng, Hsinchu, TW;
Wen-Hao Chen, Hsinchu, TW;
Yung-Sung Yen, New Taipei, TW;
Chun-Kuang Chen, Guanxi Township, TW;
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;
Abstract
The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a source region and a drain region separated by a channel region within a substrate. A middle-end-of-the-line (MEOL) structure is over the drain region and a gate structure is over the channel region. The MEOL structure is vertically disposed between the drain region and a plane extending along an upper surface of the gate structure. A first interconnect wire is connected to the MEOL structure by a first conductive contact that is directly over the drain region and that extends between the first interconnect wire and the MEOL structure. A conductive strap is located over the first interconnect wire. The conductive strap connects the first interconnect wire to a power rail having a larger width than the first interconnect wire.