The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 24, 2020

Filed:

Feb. 24, 2014
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Hongqi Li, Boise, ID (US);

Anurag Jindal, Boise, ID (US);

Jin Lu, Boise, ID (US);

Gowrisankar Damarla, Boise, ID (US);

Shyam Ramalingam, Boise, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 21/768 (2006.01); H01L 23/367 (2006.01);
U.S. Cl.
CPC ...
H01L 23/481 (2013.01); H01L 21/76897 (2013.01); H01L 21/76898 (2013.01); H01L 23/367 (2013.01); H01L 21/7682 (2013.01); H01L 21/76847 (2013.01); H01L 2924/0002 (2013.01);
Abstract

A semiconductor device in accordance with some embodiments includes a substrate structure and a conductive interconnect extending through at least a portion of the substrate structure. The conductive interconnect can include a through-silicon via and a stress-relief feature that accommodates thermal expansion and/or thermal contraction of material to manage internal stresses in the semiconductor device. Methods of manufacturing the semiconductor device in accordance with some embodiments includes removing material of the conductive interconnect to form the stress-relief gap.


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