logo

For the Inventor, By the Inventor

The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10840350 B1

PDFFull Text
Date of Patent:
Nov. 17, 2020

Filed:

Aug. 22, 2017

Nanolaminate structure, semiconductor device and method of forming nanolaminate structure

Applicants:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

The Regents of the University of California, Oakland, CA (US);

Inventors:

Zi-Wei Fang, Hsinchu County, TW;

Hong-Fa Luan, Hsinchu County, TW;

Wilman Tsai, Saratoga, CA (US);

Kasra Sardashti, La Jolla, CA (US);

Maximillian Clemons, La Jolla, CA (US);

Scott Ueda, La Jolla, CA (US);

Mahmut Kavrik, La Jolla, CA (US);

Iljo Kwak, La Jolla, CA (US);

Andrew Kummel, La Jolla, CA (US);

Hsiang-Pi Chang, New Taipei, TW;

Assignees:

TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu, TW;

THE REGENTS OF THE UNIVERSITY OF CALIFORNIA, Oakland, CA (US);

Attorney:

McClure, Qualey & Rodack, LLP

Primary Examiner:

Bitew A Dinke

Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 29/51 (2006.01); H01L 21/02 (2006.01); H01L 21/8238 (2006.01); H01L 27/092 (2006.01); H01L 29/423 (2006.01); H01L 29/78 (2006.01); H01L 29/165 (2006.01); H01L 29/94 (2006.01);
U.S. Cl.
CPC ...
H01L 29/513 (2013.01); H01L 21/022 (2013.01); H01L 21/0228 (2013.01); H01L 21/02178 (2013.01); H01L 21/02181 (2013.01); H01L 21/02192 (2013.01); H01L 21/02299 (2013.01); H01L 21/823821 (2013.01); H01L 21/823828 (2013.01); H01L 21/823857 (2013.01); H01L 27/0924 (2013.01); H01L 29/165 (2013.01); H01L 29/42364 (2013.01); H01L 29/512 (2013.01); H01L 29/517 (2013.01); H01L 29/66181 (2013.01); H01L 29/66189 (2013.01); H01L 29/66545 (2013.01); H01L 29/66636 (2013.01); H01L 29/785 (2013.01); H01L 21/02205 (2013.01); H01L 21/823807 (2013.01); H01L 29/94 (2013.01);
Abstract

The present disclosure provides a method of forming a nanolaminate structure. First, a pre-treatment is performed on a semiconductor substrate, in which the semiconductor substrate includes SiGe. Then, a first metal oxide layer is formed on the semiconductor substrate. Then, at least one second metal oxide layer and at least one third metal oxide layer are alternately stacked on the first metal oxide layer, thereby forming a nanolaminate structure. And, a conductive gate layer is formed on the nanolaminate structure.

Find Patent Forward Citations

Loading…