The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 10, 2020

Filed:

Aug. 21, 2018
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Fredrick D. Fishburn, Hiroshima, JP;

Haitao Liu, Boise, ID (US);

Soichi Sugiura, Bristow, VA (US);

Oscar O. Enomoto, Manassas, VA (US);

Mark A. Zaleski, Boise, ID (US);

Keisuke Hirofuji, Hiroshima, JP;

Makoto Morino, Tokyo, JP;

Ichiro Abe, Kanagawa, JP;

Yoshiyuki Nanjo, Hyogo, JP;

Atsuko Otsuka, Hiroshima, JP;

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/00 (2006.01); H01L 27/108 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 27/10823 (2013.01); H01L 27/10852 (2013.01); H01L 29/4236 (2013.01); H01L 29/42352 (2013.01); H01L 29/66666 (2013.01); H01L 29/66833 (2013.01);
Abstract

A semiconductor device comprises a memory storage component and a transistor in operable communication with the memory storage element. The transistor comprises a source region, a drain region, a gate electrode between the source region and the drain region, a charge trapping material surrounding at least an upper portion of the gate electrode, and an oxide material on sides of the charge trapping material. Related systems and methods are also disclosed.


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