The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 29, 2020

Filed:

Sep. 26, 2019
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Inventors:

Shih-Han Huang, Kaohsiung, TW;

Ching-Chun Wang, Tainan, TW;

Dun-Nian Yaung, Taipei, TW;

Hsing-Chih Lin, Tainan, TW;

Jen-Cheng Liu, Hsin-Chu, TW;

Min-Feng Kao, Chiayi, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/822 (2006.01); H01L 23/522 (2006.01); H01L 23/00 (2006.01); H01L 25/065 (2006.01); H01L 27/06 (2006.01); H01F 17/00 (2006.01); H01F 41/04 (2006.01); H01L 21/768 (2006.01); H01L 27/08 (2006.01); H01L 49/02 (2006.01);
U.S. Cl.
CPC ...
H01L 21/8221 (2013.01); H01F 17/0013 (2013.01); H01F 41/041 (2013.01); H01L 21/76877 (2013.01); H01L 23/5227 (2013.01); H01L 24/08 (2013.01); H01L 24/74 (2013.01); H01L 24/80 (2013.01); H01L 25/0657 (2013.01); H01L 27/0688 (2013.01); H01L 27/08 (2013.01); H01L 28/10 (2013.01); H01F 2017/002 (2013.01); H01F 2017/004 (2013.01); H01F 2017/0086 (2013.01); H01L 24/05 (2013.01); H01L 24/13 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/05558 (2013.01); H01L 2224/05647 (2013.01); H01L 2224/08146 (2013.01); H01L 2224/13101 (2013.01); H01L 2224/80895 (2013.01); H01L 2924/14 (2013.01);
Abstract

The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a first plurality of conductive interconnect layers arranged within a first inter-level dielectric (ILD) structure disposed on a first surface of a first substrate. A second plurality of conductive interconnect layers are arranged within a second ILD structure disposed on a first surface of a second substrate. The second substrate is separated from the first substrate by the first ILD structure. The first plurality of conductive interconnect layers and the second plurality of conductive interconnect layers define an inductor having one or more turns.


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