The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 15, 2020

Filed:

Oct. 25, 2018
Applicant:

Sj Semiconductor(jiangyin) Corporation, Jiangyin, CN;

Inventors:

Yenheng Chen, Jiangyin, CN;

Chengchung Lin, Jiangyin, CN;

Jangshen Lin, Jiangyin, CN;

Chengtar Wu, Jiangyin, CN;

Chihon Ho, Jiangyin, CN;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/50 (2006.01); H01L 23/66 (2006.01); H01L 23/31 (2006.01); H01L 23/48 (2006.01); H01L 23/498 (2006.01); H01L 21/48 (2006.01); H01Q 1/22 (2006.01); H01L 21/56 (2006.01);
U.S. Cl.
CPC ...
H01L 23/66 (2013.01); H01L 21/486 (2013.01); H01L 21/4853 (2013.01); H01L 21/4857 (2013.01); H01L 21/568 (2013.01); H01L 23/3128 (2013.01); H01L 23/481 (2013.01); H01L 23/49816 (2013.01); H01L 23/49822 (2013.01); H01Q 1/2283 (2013.01); H01L 2223/6677 (2013.01);
Abstract

The present disclosure provides a fan-out antenna packaging structure and a preparation method thereof. The fan-out antenna packaging structure comprises: a semiconductor chip; a plastic packaging material layer enclosing a periphery of the semiconductor chip, a via being formed in the plastic packaging material layer; a conductive pole located in the via and running through the plastic packaging material layer from top to bottom; an antenna structure located on a first surface of the plastic packaging material layer and electrically connected with the conductive pole; a redistribution layer located on a second surface of the plastic packaging material layer and electrically connected with the semiconductor chip and the conductive pole; and a solder bump located on a surface of the redistribution layer, electrically connected with the redistribution layer and insulated from the plastic packaging material layer.


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