The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 08, 2020

Filed:

Aug. 27, 2018
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Tai-Yen Peng, Hsinchu, TW;

Chang-Sheng Lin, Hsinchu County, TW;

Chien-Chung Huang, Taichung, TW;

Yu-Shu Chen, Hsinchu, TW;

Sin-Yi Yang, Taichung, TW;

Chen-Jung Wang, Hsinchu, TW;

Han-Ting Lin, Hsinchu, TW;

Chih-Yuan Ting, Taipei, TW;

Jyu-Horng Shieh, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 43/12 (2006.01); G11C 11/16 (2006.01); H01L 27/22 (2006.01); H01L 43/02 (2006.01); H01L 43/08 (2006.01); H01L 21/768 (2006.01); H01L 21/3105 (2006.01); H01L 27/24 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76819 (2013.01); H01L 21/31056 (2013.01); H01L 27/228 (2013.01); H01L 27/2436 (2013.01); H01L 43/02 (2013.01); H01L 43/12 (2013.01); H01L 21/76802 (2013.01);
Abstract

A method for fabricating an integrated circuit is provided. The method includes depositing a first polish stop layer above a memory device, in which the first polish stop layer has a first portion over the memory device and a second portion that is not over the memory device; removing the second portion of the first polish stop layer; depositing an inter-layer dielectric layer over the first polish stop layer after removing the second portion of the first polish stop layer; and polishing the inter-layer dielectric layer until reaching the first portion of the first polish stop layer.


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