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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10763260 B1

PDFFull Text
Date of Patent:
Sep. 01, 2020

Filed:

Dec. 11, 2018

Semiconductor device and method of manufacturing a semiconductor device

Applicants:

United Microelectronics Corp., Hsin-Chu, TW;

Fujian Jinhua Integrated Circuit Co., Ltd., Quanzhou, Fujian Province, CN;

Inventors:

Chien-Ting Ho, Taichung, TW;

Shih-Fang Tzou, Tainan, TW;

Chun-Yuan Wu, Yun-Lin County, TW;

Li-Wei Feng, Kaohsiung, TW;

Yu-Chieh Lin, Kaohsiung, TW;

Ying-Chiao Wang, Changhua, TW;

Tsung-Ying Tsai, Kaohsiung, TW;

Assignees:

UNITED MICROELECTRONICS CORP., Hsin-Chu, TW;

Fujian Jinhua Integrated Circuit Co., Ltd., Quanzhou, Fujian Province, CN;

Attorney:

Winston Hsu

Primary Examiner:

Asok K Sarkar

Int. Cl.
CPC ...
H01L 27/105 (2006.01); H01L 21/768 (2006.01); H01L 21/02 (2006.01); H01L 29/66 (2006.01); H01L 21/311 (2006.01); H01L 27/108 (2006.01); H01L 29/78 (2006.01); H01L 21/3105 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1052 (2013.01); H01L 21/02532 (2013.01); H01L 21/31111 (2013.01); H01L 21/76834 (2013.01); H01L 21/76846 (2013.01); H01L 21/76879 (2013.01); H01L 21/76895 (2013.01); H01L 21/76897 (2013.01); H01L 27/1085 (2013.01); H01L 27/10894 (2013.01); H01L 29/6653 (2013.01); H01L 29/6656 (2013.01); H01L 29/66575 (2013.01); H01L 29/78 (2013.01); H01L 21/31053 (2013.01);
Abstract

A semiconductor device includes a memory region, a plurality of bit lines in the memory region, a first low-k dielectric layer on each sidewall of each bit line, a plurality of storage node regions between the bit lines, and a second low-k dielectric layer surrounding each storage node region.

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