The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 25, 2020

Filed:

Apr. 22, 2019
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Chia-Cheng Chen, Hsin-Chu, TW;

Meng-Shu Lin, Hsinchu, TW;

Liang-Yin Chen, Hsinchu, TW;

Xiong-Fei Yu, Hsinchu, TW;

Syun-Ming Jang, Hsin-Chu, TW;

Hui-Cheng Chang, Tainan, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/51 (2006.01); H01L 21/8234 (2006.01); H01L 27/088 (2006.01); H01L 21/28 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/165 (2006.01);
U.S. Cl.
CPC ...
H01L 29/518 (2013.01); H01L 21/28202 (2013.01); H01L 21/823431 (2013.01); H01L 21/823462 (2013.01); H01L 27/0886 (2013.01); H01L 29/66545 (2013.01); H01L 29/7851 (2013.01); H01L 29/7856 (2013.01); H01L 29/165 (2013.01);
Abstract

An embodiment fin field-effect-transistor (finFET) includes a semiconductor fin comprising a channel region and a gate oxide on a sidewall and a top surface of the channel region. The gate oxide includes a thinnest portion having a first thickness and a thickest portion having a second thickness different than the first thickness. A difference between the first thickness and the second thickness is less than a maximum thickness variation, and the maximum thickness variation is in accordance with an operating voltage of the finFET.


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