The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 04, 2020
Filed:
Jun. 26, 2018
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Bok Eng Cheah, Bukit Gambir, MY;
Jackson Chung Peng Kong, Tanjung Tokong, MY;
Khang Choong Yong, Puchong, MY;
Yun Rou Lim, Bayan Lepas, MY;
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/49 (2006.01); H01L 23/498 (2006.01); H01L 23/00 (2006.01); H01L 21/768 (2006.01); H01L 23/538 (2006.01);
U.S. Cl.
CPC ...
H01L 23/4985 (2013.01); H01L 21/76816 (2013.01); H01L 23/5387 (2013.01); H01L 24/09 (2013.01); H01L 24/17 (2013.01); H01L 24/16 (2013.01); H01L 24/81 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/16235 (2013.01); H01L 2224/16237 (2013.01); H01L 2224/81001 (2013.01); H01L 2924/00014 (2013.01); H01L 2924/1434 (2013.01); H01L 2924/1436 (2013.01); H01L 2924/15159 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/181 (2013.01);
Abstract
A fold in a semiconductor package substrate includes an embedded device that includes orthogonal electrical coupling through the package substrate by a bond-pad via that is configured to couple to a semiconductive device that is mounted on the semiconductor package substrate. The semiconductive device is coupled to the embedded device with the orthogonal electrical coupling.