The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 28, 2020

Filed:

Apr. 06, 2018
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Tsung-Lin Yang, Hsin-Chu, TW;

Hua Feng Chen, Hsinchu, TW;

Kuei-Shun Chen, Hsinchu, TW;

Min-Yann Hsieh, Hsin-Chu, TW;

Po-Hsueh Li, Taichung, TW;

Shih-Chi Fu, Hsinchu County, TW;

Yuan-Hsiang Lung, Hsinchu, TW;

Yan-Tso Tsai, Hsin-Chu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/265 (2006.01); H01L 21/308 (2006.01); H01L 21/302 (2006.01); H01L 21/033 (2006.01); H01L 21/3213 (2006.01); H01L 21/266 (2006.01); H01L 21/306 (2006.01); H01L 21/31 (2006.01); H01L 21/311 (2006.01); H01L 21/3215 (2006.01);
U.S. Cl.
CPC ...
H01L 21/26586 (2013.01); H01L 21/0332 (2013.01); H01L 21/0337 (2013.01); H01L 21/266 (2013.01); H01L 21/2658 (2013.01); H01L 21/302 (2013.01); H01L 21/308 (2013.01); H01L 21/3081 (2013.01); H01L 21/3085 (2013.01); H01L 21/3086 (2013.01); H01L 21/30608 (2013.01); H01L 21/31 (2013.01); H01L 21/31111 (2013.01); H01L 21/32134 (2013.01); H01L 21/32155 (2013.01);
Abstract

An exemplary method includes forming a hard mask layer over an integrated circuit layer and implanting ions into a first portion of the hard mask layer without implanting ions into a second portion of the hard mask layer. An etching characteristic of the first portion is different than an etching characteristic of the second portion. After the implanting, the method includes annealing the hard mask layer. After the annealing, the method includes selectively etching the second portion of the hard mask layer, thereby forming an etching mask from the first portion of the hard mask layer. The method can further include using the etching mask to pattern the integrated circuit layer.


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