The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 21, 2020
Filed:
Jul. 26, 2019
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;
Hung-Wen Cho, Hsinchu, TW;
Fu-Jye Liang, Zhubei, TW;
Chun-Kuang Chen, Guanxi Township, Hsinchu County, TW;
Chih-Tsung Shih, Hsinchu, TW;
Li-Jui Chen, Hsinchu, TW;
Po-Chung Cheng, Zhongpu Township, Chiayi County, TW;
Chin-Hsiang Lin, Hsinchu, TW;
TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu, TW;
Abstract
A layout modification method for fabricating a semiconductor device is provided. Uniformity of critical dimensions of a first portion and a second portion in a patterned layer is calculated by using a layout for an exposure manufacturing process to produce the semiconductor device. The second portion is adjacent to the first portion, and a width of the second portion equals a penumbra size of the exposure manufacturing process. The penumbra size is utilized to indicate which area of the patterned layer is affected by light leakage exposure from another exposure manufacturing process. Non-uniformity between the first and second portions of the patterned layer is compensated according to the uniformity of critical dimensions to generate a modified layout.