The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 14, 2020
Filed:
Mar. 15, 2018
Globalfoundries Inc., Grand Cayman, KY;
Wolfgang Sauter, Burke, VT (US);
Mark W. Kuemerle, Essex Junction, VT (US);
Eric W. Tremble, Jericho, VT (US);
David B. Stone, Jericho, VT (US);
Nicholas A. Polomoff, Irvine, CA (US);
Eric S. Parent, Saratoga Springs, NY (US);
Jawahar P. Nayak, Clifton Park, NY (US);
Seungman Choi, Loudonville, NY (US);
GLOBALFOUNDRIES INC., Grand Cayman, KY;
Abstract
An IC chip structure including a plurality of IC chips electrically connected to one another in back-end-of-line (BEOL) interconnect layer of the structure is disclosed. The IC structure may include openings in crack-stop structures surrounding the IC chips and a interconnect wire extending between the IC chips through the openings. A packaging structure for utilizing the IC structure where at least one IC chip is inoperable is also disclosed. The structure may include a first bond pad array on a top surface of a packaging substrate including operable bond pads connected to an operable IC chip and structural support bond pads connected to the inoperable IC chip; a second bond pad array on a bottom surface of the substrate including operable bond pads connected to a single IC chip printed circuit board; and an interconnect structure for connecting the operable bond pads of the first and second bond pad arrays.