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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10714357 B1

PDFFull Text
Date of Patent:
Jul. 14, 2020

Filed:

Jul. 23, 2018

Methods for improved critical dimension uniformity in a semiconductor device fabrication process

Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Chi-Cheng Hung, Toufen Township, Miaoli County, TW;

Chun-Kuang Chen, Guanxi Township, Hsinchu County, TW;

De-Fang Chen, Hsinchu, TW;

Wei-Liang Lin, Hsin-Chu, TW;

Yu-Tien Shen, Hsin-Chu, TW;

Assignee:

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsin-Chu, TW;

Attorney:

Haynes and Boone, LLP

Primary Examiner:

Stephanie P Duclair

Int. Cl.
CPC ...
H01L 21/302 (2006.01); H01L 21/461 (2006.01); H01B 13/00 (2006.01); B44C 1/22 (2006.01); C03C 15/00 (2006.01); C03C 25/68 (2006.01); C23F 1/00 (2006.01); H01L 21/308 (2006.01); H01L 21/027 (2006.01); H01L 21/31 (2006.01); H01L 21/311 (2006.01); H01L 21/033 (2006.01); H01L 21/306 (2006.01); H01L 21/3065 (2006.01); G03F 7/00 (2006.01);
U.S. Cl.
CPC ...
H01L 21/3086 (2013.01); H01L 21/027 (2013.01); H01L 21/0274 (2013.01); H01L 21/0332 (2013.01); H01L 21/0337 (2013.01); H01L 21/308 (2013.01); H01L 21/3065 (2013.01); H01L 21/3081 (2013.01); H01L 21/3085 (2013.01); H01L 21/3088 (2013.01); H01L 21/30604 (2013.01); H01L 21/31 (2013.01); H01L 21/31144 (2013.01); G03F 7/0035 (2013.01);
Abstract

Exemplary methods of patterning a device layer are described, including operations of patterning a protector layer and forming a first opening in a first patterning layer to expose a first portion of the protector layer and a first portion of the hard mask layer, which are then are exposed to a first etch to form a first opening in the first portion of the hard mask layer. A second opening is formed in a second patterning layer to expose a second portion of the protector layer and a second portion of the hard mask layer. The second portion of the protector layer and the second portion of the hard mask layer are exposed to an etch to form a second opening in the second portion of the hard mask layer. Exposed portions of the device layer are then etched through the first opening and the second opening.

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