The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 16, 2020

Filed:

Aug. 23, 2016
Applicants:

Hosei University, Tokyo, JP;

Sciocs Company Limited, Hitachi-shi, Ibaraki, JP;

Sumitomo Chemical Company, Limited, Tokyo, JP;

Inventors:

Tohru Nakamura, Koganei, JP;

Tomoyoshi Mishima, Koganei, JP;

Hiroshi Ohta, Koganei, JP;

Yasuhiro Yamamoto, Koganei, JP;

Fumimasa Horikiri, Hitachi, JP;

Assignees:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/283 (2006.01); H01L 29/41 (2006.01); H01L 29/868 (2006.01); H01L 29/66 (2006.01); H01L 29/861 (2006.01); H01L 29/40 (2006.01); H01L 29/06 (2006.01); H01L 29/45 (2006.01); H01L 29/20 (2006.01);
U.S. Cl.
CPC ...
H01L 21/283 (2013.01); H01L 29/0646 (2013.01); H01L 29/0649 (2013.01); H01L 29/402 (2013.01); H01L 29/41 (2013.01); H01L 29/66204 (2013.01); H01L 29/868 (2013.01); H01L 29/8613 (2013.01); H01L 29/2003 (2013.01); H01L 29/452 (2013.01);
Abstract

A semiconductor device includes a semiconductor member having a mesa structure in which a first semiconductor layer and a second semiconductor layer are laminated on each other and having a pn junction; an insulating film disposed on a side surface of the mesa structure and on an outside upper surface of the mesa structure; a first electrode connected to the second semiconductor layer on the upper surface of the mesa structure, and extends on the side surface of the mesa structure and on the outside upper surface of the mesa structure on the insulating film; and a second electrode connected to the first semiconductor layer on a lower surface of the first semiconductor layer, and having a capacitance of the insulating film when a reverse bias voltage is applied between the first electrode and the second electrode, so that a first voltage applied to the insulating film between a corner position (a first position) where the side surface of the insulating film disposed on the side surface of the mesa structure and the upper surface of the insulating film disposed on the outside upper surface of the mesa structure are connected to each other, and a corner position (a second position) where the side surface of the mesa structure and the outside upper surface of the mesa structure are connected to each other, is equal to or smaller than a second voltage applied to the first semiconductor layer between a pn junction interface (a third position) in a lower part of a region where the first electrode is in contact with the second semiconductor layer, and a position directly under the third position (a fourth position) at a height of the second position.


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