Method for forming gate structure of three-dimensional memory device

Abstract

A method for forming a gate structure of a 3D memory device is provided. The method comprises: forming an alternating dielectric stack on a substrate; forming multiple slits, each penetrating vertically through the alternating dielectric stack and extending in a horizontal direction; removing multiple sacrificial layers in the alternating dielectric stack through the plurality of slits to form multiple trenches; forming a conductive layer in each of the trenches; forming a first isolation layer on sidewalls of the slits to cover the conductive layers to prevent the conductive layers from being oxidized; forming a second isolation layer on surfaces of the first isolation layer, a material of the second isolation layer being different from a material of the first isolation layer; and depositing a conductive material into the slits to form multiple conductive walls, the conductive walls are insulated from the conductive layers.