The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 09, 2020
Filed:
Jul. 26, 2018
Yangtze Memory Technologies Co., Ltd., Wuhan, Hubei, CN;
Jong Jun Kim, Hubei, CN;
Feng Pan, Hubei, CN;
Jong Seuk Lee, Hubei, CN;
Zhenyu Lu, Hubei, CN;
Yongna Li, Hubei, CN;
Lidong Song, Hubei, CN;
Youn Cheul Kim, Hubei, CN;
Steve Weiyi Yang, Hubei, CN;
Simon Shi-Ning Yang, Hubei, CN;
Yangtze Memory Technologies Co., Ltd., Wuhan, CN;
Abstract
Embodiments of structures and methods for testing three-dimensional (3D) memory devices are disclosed. In one example, a 3D memory device includes a memory array structure, a peripheral device structure, and an interconnect layer in contact with a front side of the memory array structure and a front side of the peripheral device structure, and a conductive pad at a back side of the memory array structure and that overlaps the memory array structure. The memory array structure includes a memory array stack, a through array contact (TAC) extending vertically through at least part of the memory array stack, and a memory array contact. The peripheral device structure includes a test circuit. The interconnect layer includes an interconnect structure. The conductive pad, the TAC, the interconnect structure, and at least one of the test circuit and the memory array contact are electrically connected.