The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 26, 2020
Filed:
Oct. 17, 2018
International Business Machines Corporation, Armonk, NY (US);
Huimei Zhou, Albany, NY (US);
Kangguo Cheng, Schenectady, NY (US);
Michael P. Belyansky, Halfmoon, NY (US);
Oleg Gluschenkov, Tannersville, NY (US);
Richard A. Conti, Altamont, NY (US);
James Kelly, Schenectady, NY (US);
Balasubramanian Pranatharthiharan, Watervliet, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
Compressive and tensile stress is induced, respectively, on semiconductor fins in the pFET and nFET regions of a monolithic semiconductor structure including FinFETs. A tensile stressor is formed from dielectric material and a second, compressive stressor is formed from metal. The stressors may be formed in fin cut regions of the monolithic semiconductor structure and are configured to provide stress in the direction of FinFET current flow. The dielectric material may be deposited on the monolithic semiconductor structure and later removed from the fin cut regions of the pFET region. Metal exhibiting compressive residual stress is then deposited in the fin cut regions from which the dielectric material was removed. Gate cut regions may also be filled with the dielectric stressor material to impart substantially uniaxial tensile stress perpendicular to the semiconductor fins and perpendicular to electrical current flow.