The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 12, 2020

Filed:

Nov. 16, 2018
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Tai-Yen Peng, Hsinchu, TW;

Chien-Chung Huang, Taichung, TW;

Yu-Shu Chen, Hsinchu, TW;

Sin-Yi Yang, Taichung, TW;

Chen-Jung Wang, Hsinchu, TW;

Han-Ting Lin, Hsinchu, TW;

Chih-Yuan Ting, Taipei, TW;

Jyu-Horng Shieh, Hsinchu, TW;

Hui-Hsien Wei, Taoyuan, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/24 (2006.01); H01L 43/12 (2006.01); H01L 27/22 (2006.01); H01L 43/02 (2006.01);
U.S. Cl.
CPC ...
H01L 43/12 (2013.01); H01L 27/224 (2013.01); H01L 27/228 (2013.01); H01L 27/222 (2013.01); H01L 43/02 (2013.01);
Abstract

A method for forming an integrated circuit is provided. The method includes forming a dielectric layer over a cell region and a logic region of a substrate; forming a resistance switching layer over the dielectric layer; performing at least one etch process to pattern the resistance switching layer into a plurality of resistance switching elements in the cell region, in which a first portion of the dielectric layer in the logic region is less etched by the etch process than a second portion of the dielectric layer in the cell region.


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