The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 05, 2020

Filed:

Sep. 10, 2018
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Chien-Ju Chao, New Taipei, TW;

Chou-Kun Lin, Hsinchu, TW;

Yi-Chuin Tsai, Sing-yan Township, TW;

Yen-Hung Lin, Hsinchu, TW;

Po-Hsiang Huang, Tainan, TW;

Kuo-Nan Yang, Hsinchu, TW;

Chung-Hsing Wang, Baoshan Township, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/06 (2006.01); H01L 27/02 (2006.01); H01L 23/528 (2006.01); H01L 23/50 (2006.01); H01L 21/768 (2006.01); H01L 21/8234 (2006.01); H01L 23/532 (2006.01); H01L 21/822 (2006.01); H01L 21/8238 (2006.01); H01L 27/092 (2006.01); H01L 21/324 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0207 (2013.01); H01L 21/768 (2013.01); H01L 21/8221 (2013.01); H01L 21/823475 (2013.01); H01L 21/823871 (2013.01); H01L 23/50 (2013.01); H01L 23/528 (2013.01); H01L 23/5283 (2013.01); H01L 23/5286 (2013.01); H01L 23/5329 (2013.01); H01L 27/0203 (2013.01); H01L 27/0688 (2013.01); H01L 27/092 (2013.01); H01L 21/324 (2013.01); H01L 23/53238 (2013.01); H01L 2924/0002 (2013.01);
Abstract

A device comprises a first interconnect structure over a first active device layer, a first power circuit in the first active device layer, a second active device layer over and in contact with the first interconnect structure, a first switch in the second active device layer, a second interconnect structure over and in contact with the second active device layer, a third active device layer over and in contact with the second interconnect structure, a second power circuit in the third active device layer and a third interconnect structure over and in contact with the third active device layer and connected to a power source, wherein the power source is configured to provide power to the first power circuit through the first switch.


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