The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 28, 2020

Filed:

May. 30, 2018
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Sasha Oster, Chandler, AZ (US);

Srikant Nekkanty, Chandler, AZ (US);

Joshua D. Heppner, Chandler, AZ (US);

Adel A. Elsherbini, Chandler, AZ (US);

Yoshihiro Tomita, Tsukuba, JP;

Debendra Mallik, Chandler, AZ (US);

Shawna M. Liff, Scottsdale, AZ (US);

Yoko Sekihara, Ibaraki, JP;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/31 (2006.01); H01L 23/367 (2006.01); H01L 23/498 (2006.01); H01L 21/56 (2006.01); H01L 23/48 (2006.01); H01L 23/58 (2006.01); H01L 23/66 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/3121 (2013.01); H01L 21/565 (2013.01); H01L 23/3675 (2013.01); H01L 23/3677 (2013.01); H01L 23/481 (2013.01); H01L 23/49811 (2013.01); H01L 23/58 (2013.01); H01L 23/66 (2013.01); H01L 24/32 (2013.01); H01L 24/83 (2013.01); H01L 24/16 (2013.01); H01L 24/81 (2013.01); H01L 2223/6677 (2013.01); H01L 2224/13101 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/81024 (2013.01); H01L 2224/81192 (2013.01); H01L 2224/81815 (2013.01); H01L 2224/8385 (2013.01); H01L 2224/83801 (2013.01); H01L 2924/10253 (2013.01); H01L 2924/10329 (2013.01); H01L 2924/1433 (2013.01); H01L 2924/181 (2013.01);
Abstract

Examples of an electronic package include a package assembly. The package assembly can include a substrate having a first substrate surface that includes a conductive layer attached to the first substrate surface. The package assembly includes a die communicatively coupled to the conductive layer and a contact block that includes a first contact surface on one end of the contact block, a second contact surface on an opposing side of the contact block, and a contact block wall extended therebetween. The contact block can include a conductive material. The first contact surface can be coupled to the package assembly with a joint extended partially up the contact block wall. The electronic package can further include an overmold covering portions of the substrate, conductive layer, and die. The second contact surface of the contact block can be exposed through the overmold.


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