The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 21, 2020
Filed:
May. 25, 2018
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;
Kong-Beng Thei, Pao-Shan Village, TW;
Dun-Nian Yaung, Taipei, TW;
Fu-Jier Fan, Hsinchu, TW;
Hsing-Chih Lin, Tainan, TW;
Hsiao-Chin Tuan, Taowan, TW;
Jen-Cheng Liu, Hsin-Chu, TW;
Alexander Kalnitsky, San Francisco, CA (US);
Yi-Sheng Chen, Hsinchu, TW;
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;
Abstract
A three-dimensional (3D) integrated circuit (IC) is provided. In some embodiments, a first IC die comprises a first bonding structure and a first interconnect structure over a first semiconductor substrate. A second IC die is disposed over the first IC die and comprises a second bonding structure and a second interconnect structure over a second semiconductor substrate. A seal-ring structure is in the first and second IC dies and extends from the first semiconductor substrate to the second semiconductor substrate. A plurality of through silicon via (TSV) coupling structures is arranged in the peripheral region of the 3D IC along an inner perimeter of the seal-ring structure. The plurality of TSV coupling structures respectively comprises a through silicon via (TSV) disposed in the second semiconductor substrate and electrically coupling to the 3D IC through a stack of TSV wiring layers and inter-wire vias.