The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 07, 2020

Filed:

May. 30, 2018
Applicants:

Global Unichip Corporation, Hsinchu, TW;

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Meng-Hsiu Tsai, Hsinchu, TW;

Hsin-Hsiung Liao, Hsinchu, TW;

Min-Hsiu Tsai, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); G06F 30/3312 (2020.01); G06F 30/327 (2020.01); G06F 111/20 (2020.01); G06F 119/12 (2020.01);
U.S. Cl.
CPC ...
G06F 30/3312 (2020.01); G06F 30/327 (2020.01); G06F 2111/20 (2020.01); G06F 2119/12 (2020.01);
Abstract

A model-building method comprises following operations: reading a top netlist and a block model, wherein the top netlist comprises a first input node, a first output node and a multivibrator, the block model comprises a input node and a output node; obtaining a first subnetlist from the top netlist, wherein the first subnetlist comprises a component coupled between the input node and the first input node or the multivibrator; obtaining a second subnetlist from the top netlist, wherein the second subnetlist comprises a component coupled between the output node and the first output node or the multivibrator; obtaining a third subnetlist from the top netlist, wherein the third subnetlist comprises a component coupled between a clock input node of the multivibrator and a top clock input node of the top netlist; generating a top ILM according to the first to the third subnetlist.


Find Patent Forward Citations

Tsai, Meng-Hsiu. (2020). Model-building method for building top interface logic model (U.S. Patent No. 10614260). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10614260

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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