The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10586715 B1

PDF
Full Text
Expired
Date of Patent:
Mar. 10, 2020

Filed:

May. 05, 2017
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Yonggang Yong Li, Chandler, AZ (US);

Aritra Dhar, Tempe, AZ (US);

Dilan Seneviratne, Chandler, AZ (US);

Jon M. Williams, Gilbert, AZ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/288 (2006.01); H01L 21/48 (2006.01); H01L 23/498 (2006.01); C23C 18/16 (2006.01); C23C 18/38 (2006.01); C23C 18/20 (2006.01); C23C 18/30 (2006.01); H05K 3/10 (2006.01); H05K 3/18 (2006.01); H05K 3/00 (2006.01); H05K 3/04 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 21/4857 (2013.01); C23C 18/1608 (2013.01); C23C 18/1612 (2013.01); C23C 18/2086 (2013.01); C23C 18/30 (2013.01); C23C 18/38 (2013.01); H01L 21/288 (2013.01); H01L 21/486 (2013.01); H01L 21/4864 (2013.01); H01L 23/49822 (2013.01); H01L 23/49827 (2013.01); H01L 23/49838 (2013.01); H01L 23/49866 (2013.01); H05K 3/107 (2013.01); H05K 3/185 (2013.01); H01L 24/17 (2013.01); H01L 2224/16225 (2013.01); H01L 2924/15311 (2013.01); H05K 3/0032 (2013.01); H05K 3/045 (2013.01); H05K 2201/0236 (2013.01); H05K 2203/072 (2013.01); H05K 2203/107 (2013.01);
Abstract

Embodiments describe the selective electroless plating of dielectric layers. According to an embodiment, a dielectric layer is patterned to form one or more patterned surfaces. A seed layer is then selectively formed along the patterned surfaces of the dielectric layer. An electroless plating process is used to deposit metal only on the patterned surfaces of the dielectric layer. According to an embodiment, the dielectric layer is doped with an activator precursor. Laser assisted local activation is performed on the patterned surfaces of the dielectric layer in order to selectively form a seed layer only on the patterned surfaces of the dielectric layer by reducing the activator precursor to an oxidation state of zero. According to an additional embodiment, a seed layer is selectively formed on the patterned surfaces of the dielectric layer with a colloidal or ionic seeding solution.


Find Patent Forward Citations

Li, Yonggang. (2020). Embedded circuit patterning feature selective electroless (U.S. Patent No. 10586715). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10586715

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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