The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 03, 2020

Filed:

Jul. 30, 2018
Applicant:

Winbond Electronics Corp., Taichung, TW;

Inventors:

Chiang-Hung Chen, Taichung, TW;

Yao-Ting Tsai, Taichung, TW;

Wen Hung, Taichung, TW;

Yu-Kai Liao, Taichung, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/56 (2006.01); H01L 21/3215 (2006.01); H01L 23/532 (2006.01); H01L 29/51 (2006.01); G11C 16/10 (2006.01); G11C 16/14 (2006.01); G11C 16/26 (2006.01); H01L 27/11582 (2017.01); G11C 16/04 (2006.01); H01L 21/762 (2006.01); H01L 21/3105 (2006.01); H01L 21/768 (2006.01); H01L 21/02 (2006.01); H01L 21/311 (2006.01); H01L 21/3213 (2006.01); H01L 23/528 (2006.01); H01L 21/28 (2006.01); H01L 29/423 (2006.01); H01L 27/11521 (2017.01); H01L 29/66 (2006.01); H01L 29/788 (2006.01);
U.S. Cl.
CPC ...
G11C 11/5671 (2013.01); G11C 16/0466 (2013.01); G11C 16/0483 (2013.01); G11C 16/10 (2013.01); G11C 16/14 (2013.01); G11C 16/26 (2013.01); H01L 21/0217 (2013.01); H01L 21/02164 (2013.01); H01L 21/02271 (2013.01); H01L 21/31053 (2013.01); H01L 21/31111 (2013.01); H01L 21/31116 (2013.01); H01L 21/32135 (2013.01); H01L 21/32155 (2013.01); H01L 21/7684 (2013.01); H01L 21/76224 (2013.01); H01L 21/76283 (2013.01); H01L 21/76877 (2013.01); H01L 23/528 (2013.01); H01L 23/53271 (2013.01); H01L 27/11521 (2013.01); H01L 27/11582 (2013.01); H01L 29/40117 (2019.08); H01L 29/42324 (2013.01); H01L 29/517 (2013.01); H01L 29/518 (2013.01); H01L 29/66825 (2013.01); H01L 29/7881 (2013.01); H01L 29/7889 (2013.01);
Abstract

A three dimensional memory includes a substrate, a plurality of source lines, a plurality of isolation structures, a plurality of drain lines, a plurality of bit lines, a plurality of charge storage structures, and a plurality of conductive layers. The source lines are located on the substrate. The isolation structures are respectively located between the source lines, so as to electrically isolate the source lines from each other. The drain lines are located on the source lines. Extending directions of the source lines and the drain lines are different. The bit lines extend from the source lines to the drain lines. The charge storage structures respectively surround the bit lines. The conductive layers respectively cover surfaces of the charge storage structures arranged along each of the source lines.


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