The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 25, 2020

Filed:

Aug. 08, 2018
Applicant:

Infineon Technologies Austria Ag, Villach, AT;

Inventors:

Thomas Feil, Villach, AT;

Robert Haase, San Pedro, CA (US);

Martin Poelzl, Ossiach, AT;

Maximilian Roesch, St. Magdalen, AT;

Sylvain Leomant, Poertschach am Woerthersee, AT;

Bernhard Goller, Villach, AT;

Ravi Keshav Joshi, Klagenfurt, AT;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 21/28 (2006.01); H01L 29/78 (2006.01); H01L 29/08 (2006.01); H01L 29/10 (2006.01); H01L 29/423 (2006.01); H01L 29/51 (2006.01); H01L 29/40 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7813 (2013.01); H01L 21/28167 (2013.01); H01L 29/0856 (2013.01); H01L 29/1033 (2013.01); H01L 29/1095 (2013.01); H01L 29/407 (2013.01); H01L 29/4236 (2013.01); H01L 29/513 (2013.01); H01L 29/66734 (2013.01);
Abstract

A semiconductor device includes a gate trench extending into a Si substrate, a body region in the Si substrate adjacent the gate trench, a source region in the Si substrate above the body region, a contact trench extending into the Si substrate and filled with an electrically conductive material which contacts the source region at a sidewall of the contact trench and a highly doped body contact region at a bottom of the contact trench, a diffusion barrier structure formed along the sidewall of the gate trench, the diffusion barrier structure comprising alternating layers of Si and oxygen-doped Si and a Si capping layer on the alternating layers of Si and oxygen-doped Si, and a channel region formed in the Si capping layer and which vertically extends along the sidewall of the gate trench. Corresponding methods of manufacture are also described.


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