The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 18, 2020
Filed:
Apr. 30, 2018
Globalfoundries Inc., Grand Cayman, KY;
Martin J. O'Toole, Saratoga Springs, NY (US);
Christopher J. Penny, Saratoga Springs, NY (US);
Jae O. Choo, Clifton Park, NY (US);
Adam L. da Silva, Saratoga Springs, NY (US);
Craig Child, Gansevoort, NY (US);
Terry A. Spooner, Halfmoon, NY (US);
Hsueh-Chung Chen, Cohoes, NY (US);
Brendan O'Brien, Ballston Spa, NY (US);
Keith P. Donegan, Saratoga Springs, NY (US);
GLOBALFOUNDRIES INC., Grand Cayman, KY;
Abstract
Methods of forming an interconnect of an IC are disclosed. The methods include forming a first interlayer dielectric (ILD) layer and a second ILD layer with an ILD etch stop layer (ESL) therebetween. The ILD ESL has an etch rate that is at least five times slower than the first and second ILD layers, and may include, for example, aluminum oxynitride. A dual damascene (DD) hard mask is used to form a wire trench opening in the second ILD layer and a via opening in the first ILD layer, creating a via-wire opening. Due to the slower etch rate, the ILD ESL defines the via opening in the first ILD layer as a chamferless via opening. A unitary via-wire conductive structure coupled to the conductive structure in the via-wire opening can be formed from the via-wire opening.