The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 07, 2020

Filed:

Nov. 18, 2016
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Yu-Chang Lin, Hsin-Chu, TW;

Wei-Ting Chien, Hsin-Chu, TW;

Chun-Feng Nieh, Hsin-Chu, TW;

Wen-Li Chiu, Kaohsiung, TW;

Huicheng Chang, Tainan, TW;

Chun-Sheng Liang, Puyan Township, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 29/417 (2006.01); H01L 29/16 (2006.01); H01L 29/10 (2006.01); H01L 21/3115 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7851 (2013.01); H01L 21/31155 (2013.01); H01L 29/1054 (2013.01); H01L 29/16 (2013.01); H01L 29/41758 (2013.01); H01L 29/66795 (2013.01);
Abstract

FinFET structures and methods of forming the same are disclosed. A device includes a semiconductor fin. A gate stack is on the semiconductor fin. The gate stack includes a gate dielectric on the semiconductor fin and a gate electrode on the gate dielectric. The gate electrode and the gate dielectric have top surfaces level with one another. A first inter-layer dielectric (ILD) is adjacent the gate stack over the semiconductor fin. The first ILD exerts a compressive strain on the gate stack.


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